1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to the configuration of a memory array portion in a semiconductor memory device of a multi-bank configuration having a plurality of banks.
2. Description of the Background Art
As higher function microprocessors have been developed recently, there are increasing needs for specifications which permit mass storage a capacity and high speed accessing in the field of semiconductor memory devices. In order to meet these needs for achieving higher function for the devices, DRAMs of a so-called multi-bank configuration having a plurality of banks and capable of operating these banks in a multiplied manner have been implemented.
Conventional Device 1
A DRAM of a multi-bank configuration is for example disclosed by Yoo et al, "A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 Gbyte/s Bandwidth", IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996, pp. 1635 to 1642 (hereinafter referred to as "Conventional Art 1").
FIG. 19 is a schematic diagram of the configuration of a memory cell array portion in a DRAM 2000 of a multi-bank configuration according to Conventional Art 1.
Referring to FIG. 19, the memory cell array portion includes a memory cell array 500, a row decoder 520 and a column decoder 530. Memory cell array 500 is divided into 8 banks in the direction orthogonal to the column-direction, and each bank includes sub arrays 510. Each of the sub arrays includes memory cells for holding data.
Multi-bank DRAM 2000 activates a bank including a memory cell selected in response to an address signal, and reads/writes data from/to the selected memory cell by row decoder 520 and column decoder 530.
FIG. 20 is a diagram showing in detail the configuration of sub array 510. In FIG. 20, the shadowed portion in FIG. 19 is illustrated in detail.
Referring to FIG. 20, sub array 510 includes sense amplifiers 540 on both regions adjacent to a subblock in the column direction. A memory cell identified by an address signal in sub array 510 is selected by a word line activated by row decoder 520 and a column line activated by column decoder 530.
Herein, all the memory cells having the same row address are included in the same bank, one word line is provided for each row address. For the column addresses, the memory cells having the same column address are present in different banks.
As a result, in selecting a column line, a global column selecting line (GCSL) 560 and a local column selecting line (LCSL) 570 are both necessary for each of the column addresses. A local column decoder (LCD) 550 is provided corresponding to each sub array to drive local column selecting line (LCSL) 570 into a selected state.
Data in a memory cell connected to a word line driven into a selected state is amplified by sense amplifier 540, and then read out onto a local I/O line 580 according to the activation of local column selecting line 570. Local I/O line 580 is connected to a global I/O line 590 through an I/O selecting circuit 600. I/O selecting circuit 600 transmits the data on local I/O line 580 at the activated bank to global I/O line 590.
Through the above-described operations, the plurality of banks included in memory cell array 500 may each perform a data processing independently from one another, such that high processing capability is achieved. However, since the column selecting lines should be provided in a hierarchical arrangement as described above, several problems as follows are encountered.
FIG. 21 is a diagram for illustrating the configuration of local column decoder (LCD) 550. Referring to FIG. 21, global column selecting line GCSL is a common signal line for all the banks, and activated in a column including an addressed memory cell. Meanwhile, local column selecting line LCSL is effective only in each respective bank.
Local column selecting line LCSL is connected to global column selecting line GCSL by a transistor 610 receiving at its gate a BANK signal line 630 which transmits a signal (BANK signal) indicating the selected state of a bank. Local column selecting line LCSL is also connected to a ground potential by a transistor 620 receiving at its gate a /BANK signal line 640 which transmits the inverse of the BANK signal.
Local column decoder (LCD) 550 drives local column selecting line LCSL into a selected state (at an "H" level) if global column selecting line GCSL and BANK signal line 630 are both activated (into an "H" level).
The potential of local column selecting line 570 in the selected state, however, corresponds to a value produced by subtracting the threshold value of transistor 610 connected between the local and global column selecting lines from the potential corresponding to the activated state of global selecting line 560. A bit line onto which data in the addressed memory cell is read out is connected to local I/O line 580 through a transistor (not shown) receiving at its gate the local column selecting line, and therefore the resulting final potential on local I/O line 580 is lower than the initial potential. As a result, the potential corresponding to the "H" level of the data could be lower than enough. In order to solve this drawback, if the potential of the BANK signal line in the activated state (at an "H" level) is raised by the amount of the threshold voltage of N-type transistor 610, the power consumption could further increase.
All the memory cells having the same row address in memory cell 500 belong to the same bank, and are connected to a single main word line. As a result, for a single row selecting operation, the sense amplifiers corresponding to all the memory cells included in the same one row should be activated, which impedes a reduction in the power consumption.
Conventional Art 2
In order to eliminate the above-described disadvantages, Japanese Patent Laying-Open No. 9-73776 discloses the configuration of a multi-bank DRAM in which each bank is divided in the direction orthogonal to the row-direction (hereinafter referred to as "Conventional Art 2").
FIG. 22 is a schematic diagram of the configuration of a memory cell array portion in a DRAM 3000 of a multi-bank configuration according to Conventional Art 2.
Referring to FIG. 22, the memory cell array portion includes a memory cell array 500, a row decoder 520, a word line driver 525, and a column decoder 530. Memory cell array 500 is divided into 8 banks in the direction orthogonal to the column-direction, and each bank includes sub arrays 510.
Memory cell array 500 includes 4 banks separated in the column-direction. Each bank is further divided into sub arrays 510. Sub array 510 includes a plurality of memory cells for storing data.
In multi-bank DRAM 3000, memory cells having the same column address are included in the same bank, and the banks include sub column decoders 531 to 534. A column selecting line 700 needs only be provided on a column-basis. Therefore, unlike multi-bank DRAM 2000 described above, the lowering of the potential level during transmitting stored data onto the I/O line caused by the hierarchical arrangement of the column selecting lines is not encountered.
FIG. 23 is a diagram showing the arrangement of word selecting lines in multi-bank DRAM 3000.
Referring to FIG. 23, multi-bank DRAM 3000 includes a main word line 710 provided corresponding to each row as a common signal line to all the banks in order to select a memory cell at a designated row address, a sub word line 720 for selecting a corresponding row in the same bank, and a logic gate 730 which associates main word line 710 and sub-word line 720.
Main word line 710 is connected with the sub word line 720 of each bank through logic gate 730. Logic gate 730 is provided for each row in each bank, and receives main word line 710 and bank selecting signals B1 to B4. Logic gate 730 takes the logical product of the main word line and the bank selecting signal, to bring, into a selected state, a sub word line corresponding to main word line 710 in an activated state in a selected bank and initiates the operation of reading out data.
FIG. 24 is a schematic diagram of the configuration of the periphery of sense amplifiers in multi-bank DRAM 3000. Referring to FIG. 24, sense amplifier 800 is connected with a bit line pair BL, /BL through transistor gates 770 and 780, and is activated by sense amplifier activation signals SPN1 to SPN4.
Transistor gates 770 and 780 receive at their gates signals BIU1 to BIU4 and BIL1 to BIL4, and connect or disconnect between bit line pair BL, /BL and sense amplifier 800 based on the state of these signals.
In a selected bank, data in a memory cell read out on bit line pair BL, /BL by sub word line 720 is amplified by sense amplifier 800. The amplified data is transmitted to a global I/O line (not shown) based on the state of bank selecting signals B1 to B4 through a local I/O line.
In multi-bank DRAM 3000, since the bank configuration divided in the column-direction is employed, only the memory cells belonging to the same bank among the memory cells having the same row address need only be selected in a single row selecting operation. As a result, the number of memory cells and sense amplifiers activated in a single row selecting operation are smaller than the case of multi-bank DRAM 2000 according to Conventional Art 1.
As a result, multi-bank DRAM 3000 achieves high data processing capability by driving a plurality of banks independently from one another while reducing the power consumption.
Multi-bank DRAM 3000 however should transmit, to the corresponding banks, all the signals to control a row selecting operation such as sense amplifier activation signals SPM1 to SPM4, and BL selecting signals BIU1 to BIU4 and BIL1 to BIL4 in a corresponding manner.
As a result, despite the above-described advantages, the number of signal lines provided in the row-direction is considerably large. Such increase in the number of signal lines could reduce the distances between the signal lines, which increases line capacitance. Accordingly, faults such as signal delay or short circuit could be frequently caused.
In multi-bank DRAM 3000, sub word lines are driven into a selected state by directly associating the activated states of bank selecting signals B1 to B4 and main word line 710, and therefore a fault may be caused if memory cells belonging to different banks are selected at the same timing.
Referring back to FIG. 23, the disadvantage will be detailed.
Let us now assume that a memory cell MCa in the first row in bank #1 is selected, and then a memory cell MCb in the second row in bank #4 is selected. For selecting MCa, bank selecting signal B1 and main word line MW1 should be activated. Herein, until data in memory cell MCa is finally transmitted onto the global I/O line, the activated state of bank selecting signal B1 should be maintained.
Meanwhile, if the next operation of selecting memory cell MCb is to be initiated, bank selecting signal B4 and main word line MWL2 should be activated. At this time, since bank selecting signal B1 is maintained in the activated state, sub word line SWL21 is driven into a selected state corresponding to the activation of main word line MWL2.
Memory cell MCc is thus activated as well, in other words, a plurality of memory cells row-selected could be connected to the same bit line. This could cause destruction of data depending upon the timing, which poses a serious problem to the stability of the operation of the DRAM.